1. Field of the Invention
The invention relates to the field of electronic circuits. More particularly, the invention relates to the field of oscillators and phase locked loops (PLLs).
2. Description of Related Art
Phase and frequency controlled oscillators are used in a variety of electronic applications to provide stable, controlled, frequency references. A digital device may use a frequency controlled oscillator as a clock source for timing, for example, as a clock for a digital microprocessor circuit. An analog device may include a phase locked oscillator as a local oscillator used to frequency convert Radio Frequency (RF) signals. The phase and frequency controlled oscillator may be fixed frequency oscillator or may be a tunable oscillator that is implemented using a programmable frequency synthesizer.
A frequency controlled oscillator for a digital device may be implemented digitally, while a phase locked oscillator for an analog device may be implemented using exclusively analog building blocks. However, as the operating speeds of digital circuits increase, it is becoming more feasible to implement at least portions of a phase locked oscillator for traditionally analog applications using digital building blocks.
Some of the improvements in the operating speeds of digital circuits can be attributable to improvements in the processes uses to manufacture the digital circuits. Improvements in processes that shrink the size of the underlying transistors utilized in digital integrated circuit designs are related to improvements in operating speeds. CMOS circuits may be implemented using sub-micron processes, such as 90 nm, 65 nm, 45 nm, or 35 nm processes.
The supply voltage utilized in CMOS circuits have continually decreased due in part to decreases in dimensions and also due in part to desires to reduce the overall power consumed by such devices. In advanced CMOS processes, such as 65 nm, the power supply voltage is typically reduced to around 1.1V. At this low voltage, conventional analog building blocks such as operation amplifiers and current mirrors don't work well and are difficult to design. Thus, a conventional analog PLL is difficult to design with such process. In addition, an analog PLL typically needs large area to implement a filter function, while at 65 nm, silicon unit area is more expensive than die area for larger processes.
The advancements in digital processes result in greater constraints on the ability to implement traditional analog circuits, such as a PLL. Additionally, the advanced digital processes make traditional analog implementations more expensive. It is desirable to capitalize on the process improvements in the digital domain while minimizing the negative effects on circuits traditionally implemented using analog building blocks.